Driven largely by the growing need for more data, increased functionality, and faster speeds, consumer electronic devices have sparked a revolution in integrated circuit (IC) design. As it becomes increasingly more expensive and technically challenging to scale down semiconductor devices, Moore's law is yielding to the concept of “More than Moore,” which is driving integrated functionality in smaller and thinner packages. Packaging for 2.5D and 3D ICs has become critical to new products requiring higher performance and increased functionality in a smaller package. The use of a Through Silicon Via (TSV) has been discussed as a method for stacking die to achieve a vertical interconnect. However, the high costs associated with this technology have limited TSV use to a few applications such as high-bandwidth memory and logic, slowing its adoption within the industry to only those applications that obtain a premium price for the superior performance of TSV architecture. Those applications requiring enhanced performance but unable to support premium pricing in the marketplace require alternate solutions. As such, there is a need for alternatives to the TSV architecture.
IC wafers, which typically are in the form of flat round disks (although other shapes are possible) and often are made from silicon, gallium arsenide, or other materials, may be processed using various chemicals. To finish the manufacturing process of the IC wafers, the silicon (or other material) must be thinned without damaging the remaining elements of the IC wafer. Conventional processes for thinning wafers involves grinding to remove the bulk of the wafer and a multistep sequence of processes that includes chemical mechanical planarization (CMP) and plasma etching to complete the final thinning of the wafer. However, these conventional processes have a number of disadvantages associated therewith including but not limited to the complexity of the processes and the associated costs. As such, there is also a need for cost-effective alternative processes for thinning the IC wafers.
As described hereinafter, the present invention is directed at overcoming deficiencies associated with conventional IC designs and conventional wafer thinning processes.